Logic Synthesis Using Synopsis

Rating:
Summary: This is the book I was looking for...sensational!!
Review: A must for any engineer making a transition from schematic capture to VHDL or Verilog using synopsys..A MUST have book for the library!!.

Rating:
Summary: It's a book for how to using design compiler
Review: In the book, the author explained methods to use synopsys synthesis tool kit in detail.

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Summary: too expensive...would have bought if Dover published it..
Review: learn logic synthesis == Himanshu Bhatnagar
Use logic synthesis on real word designs == synopsys reference manuals
develop logic synthesis == fabio somenzi and gary hachtel or srinivas devadas and kurt keutzer

Personally the people who can constrain their design's best are logic designers and people who can delve deeper into the tool are algorithm developers themselves (and those guys dont have so much time!). These half wits will end up killing you...

Rating:
Summary: Illinois reader
Review: Provides some real insights into how to use Synopsys for synthesis efficiently and effectively. Even though the price is high, its worht sitting on your shelf. Although I do love the book, please be advised the book is a little dry in its reading. Some of the descriptions in the text are not explained very well. It seems more like a copy-paste job then a real text. However, a must buy for anyone interested in ASIC.