Design for AT-Speed Test, Diagnosis and Measurement (FRONTIERS IN ELECTRONIC TESTING Volume 15)

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Summary: The practical ABCs of embedded test
Review: Design for at-speed test, diagnosis and measurement. As a concept, it remains controversial. As a practical technique, designers at many leading-edge companies immerse themselves in it every day. As the title of a newly-published Kluwer book, it is a manual for the True Believer. True, Design for At-Speed Test, Diagnosis and Measurement-the book-is the test gospel according to LogicVision, the guiding force behind the text. True, LogicVision developed much of the technology detailed in its eight chapters. True, LogicVision owns and markets much of the technology. But LogicVision almost single handedly paved the path to commercialized embedded test and, except for Fluence Technology, Mentor Graphics and a few others specializing mainly in memory BIST, is almost alone on that road, even today. Unlike other texts on designing for testability, this is not a theoretical tome. It is a practical guide, aimed at designers, product managers and test engineers. The technology described has been proven in silicon, not merely in the lab but by the likes of Cabletron, Cisco Systems, Ericsson, Fujitsu, Hughes, Lockheed-Martin, LSI Logic, National Semiconductor, Nortel Networks, Stratus and Sun Microsystems. Truly a sterling lineup of believers. Many of these companies have learned that test no longer is a back-end problem, and that yield, quality, reliability, cost and time to market depend on test. Many also have learned that external test alone cannot do the job. Two of the reasons for that are the rise of systems on silicon and the need to test chips at their intended operating frequencies. With the former, diminishing access to internal nodes or functional blocks fundamentally points to an embedded test solution; with the latter, the spreading gap between on-chip operating frequencies and maximum external tester frequency and accuracy point to the same solution. The book, edited by Benoit Nadeau-Dostie, LogicVision's chief scientist, illuminates at-speed testing as a way to perform tests, diagnose failures, and make measurements using system clocks. Testing chips at or close to normal operation directly affects the number of chips found to be defective during system operation, yet pass all manufacturing and functional tests. Through contributions from nine experts, working for or associated with LogicVision, Design for At-Speed Test dispels one of the stubborn myths about embedded test-the inability to move beyond the simple pass/fail test. Of course, diagnosing failures is essential, and the book not only describes several levels of diagnostic features but how to accurately measure circuit parameters in data converters and phase-locked loops. Other issues are answered, or at least addressed, in the quest for practical implementation of embedded test. What restrictions are placed on chip or system design styles? How is performance affected? What about skew and timing issues? How are tests verified and debugged? Starting with a technology overview, the book launches into memory test and diagnosis, flows into logic test and diagnosis, describes the three phases involved in inserting embedded test, shimmies over to the growing question of how to handle embedded cores within a hierarchy (including legacy cores), segways to measuring on-chip parameters of converters and PLLs, and finally reaches the top: system test and diagnosis and system reuse of embedded test. Still learning about on-chip test? Start at the back, where a ten-page glossary defines the terms, from A to Z.

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Summary: Book Review on Design for At-Speed Test, Diagnosis and Measu
Review: One of the newest titles from the Kluwer Academic Publishers, Design for At-Speed Test, Diagnosis and Measurement, will be available to the chip design and test community starting at ITC'99 in Atlantic City. The book offers a valuable addition to the growing body of literature discussing design-for-test (DFT) tools, specifically embedded test solutions that travel with the functional chip and which offer the appeal of at-speed testing. In this emerging era of system-on-a-chip (SOC) design, with its companion pressures for decreased time to market and increased product quality and reliability, the various technologies discussed in the text will prove extremely useful and possibly crucial to system success at tape-out and beyond.

The book essentially arises out of the cutting-edge technologies emerging from LogicVision, Inc. of San Jose, Calif. Vinod Agarwal, president and CEO of the company, worked with Kluwer to refine the contents of the publication and set the overall direction for the material. Principal editor Benoit Nadeau-Dostie, chief scientist for LogicVision, was assisted in the compilation effort by, among others, various members of the IEEE 1149.5 and IEEE 1500 working groups and task forces (including Yervant Zorian, chair of IEEE 1500). Not surprisingly, it is those technologies that have emerged from the development staff at LogicVision that figure most prominently in the text. However, the solutions offered by other companies in the field are referenced as well (including offerings from ASSET InterTech, Intellitech, Corelis, and Teradyne) along with concise descriptions of strategies for integrating the solutions from these various companies and those from LogicVision into a unified design flow.

The material is presented in a clear and orderly manner, starting with a technology overview, followed by in-depth discussions of memory and logic built-in self test (BIST) strategies, as well as embedded block and overall core test flows. These topics are particularly relevant to the myriad companies currently ramping up their expertise in reusable IP, both IP generated in-house and that provided by third-party entities. The concepts fundamental to IP reuse and SOC design optimization-although intuitively clear-remain extremely complex and therefore challenging to implement. These concepts are discussed in depth and present a cogent overview of the current thinking in the industry. The chapter on PLLs and ADCs is particularly useful in its detail and presentation. The tools and technologies laid out in the text will help designers and manufacturers to fully comprehend the concepts that are key to successful implementation of embedded test circuitry, thus helping to guarantee the post-tape-out testability of the chips currently under development.

Much of this material has only been available up to this point in academic publications and conference proceedings. To have the material summarized and presented in this fashion aids the design and manufacturer community by presenting this discussion of current trends and technologies under one cover. As there are a multitude of concepts that need to be grasped at some level by designers and manufacturers-some of which extend beyond the daily scope of their workthe book includes clearly written material on a variety of topics relevant to embedded test implementation. The illustrations are excellent. The many references to recent papers presented at the end of each chapter provide a useful starting point for those interested in pursuing various ideas in greater detail.

The book can, therefore, be used as a high-level overview of the many important concepts behind the technology, or as a very specific and detailed guide for implementing those technologies. Either way, the reader will find the book a valuable aid going forward in the face of the Millenium's challenges for system on a chip and IP reuse. It would not be surprising to find the book-perhaps minus the specific references to any particular company's product offerings-reworked as a college text complete with end-of-chapter review questions and solutions. The book would work effectively in that setting. Peggy Aycinena, Managing Editor, ISD Magazine

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Summary: Lacking in DFT concepts
Review: With recent advances in semi conductor process technology companies that design and manufacture leading edge products are quickly moving towards deep sub micron (DSM) integrated circuits (IC) technology. This transition occurs because DSM technology enables increased functionality, higher chip performance and decreased costs.

One obstacle to achieving the full benefits of a DSM technology is the inability of today's design and test methodologies to keep up with continual advances in semi conductor process development. As more companies experience the testing challenges imposed b DSM technology, there is a growing acceptance that semi conductor designers and manufacturers must use a hierarchal approach to testing. Leading manufacturers/developers of semi conductor products are adopting hierarchal test solution - embedded test. Embedded test extends conventional test method with a test solution that hierarchally embeds critical portion of the ATE into the product itself. This embedded test critical portions of the ATE into the product itself. This embedded test complements the functionality of the external ATE and addresses the complexity of products based on technology.

This text provides the application of one such vendor -Logic Vision. If the reader is in search of in-depth embedded test application knowledge in DFT, MBIST, LBIST and JTAG then this is not a recommended book, as this is a handy reference manual to Logic Vision tools.