Rating: 
Summary: good learning and reference book for beginners
Review: so far, the best verilog book i've used. easy reference with many examples.
Rating: 
Summary: Warning about Verilog 2001
Review: The 2nd Edition of this book should be renamed, "Verilog 2001 HDL". Palnitkar added Verilog 2001 to this edition but neglected to mention the difference between Verilog and Verilog 2001 in his text. For example in his 2nd edition he says that arrays can be declared with any number of dimensions. But he fails to add that is only true for Verilog 2001. Many simulators and synthesis tools don't support all of verilog 2001 yet so you may have trouble getting the example code working in a real design.
Rating:
Summary: Very good book for beginners and experienced users
Review: The book takes you through the Verilog HDL language in a very systematic way. The presentation and examples are very self explanatory. Very good for people who are new to the language and can be quite helpful to experienced programmers who want a quick reference. The demo simulator is not much, but great to simulate small designs.
Rating:
Summary: A Mixed Bag of verilog
Review: The early chapters are an excellent guide to the syntax and wiring connections, they clearly outline potential pitfalls. Chapters 5 & 6 cover designs from too low a level. I'm sure other real-world designers will agree that modeling a flip-flop with gates just flops. I'm on Ch. 7 now and except for a reference on (min:typ:max) back to (yech!) chapter 5 the author finally gets back to real world design and synthesis (though he doesn't differentiate). Design for synthesis is a different animal than test design and where they diverge should be hi-lighted. But the explanations are clear and eventually the important levels of verilog design are covered. So if read thoughtfully it is a very good intro to verilog, but beware the useless filler.
Rating:
Summary: A Mixed Bag of verilog
Review: The early chapters are an excellent guide to the syntax and wiring connections, they clearly outline potential pitfalls. Chapters 5 & 6 cover designs from too low a level. I'm sure other real-world designers will agree that modeling a flip-flop with gates just flops. I'm on Ch. 7 now and except for a reference on (min:typ:max) back to (yech!) chapter 5 the author finally gets back to real world design and synthesis (though he doesn't differentiate). Design for synthesis is a different animal than test design and where they diverge should be hi-lighted. But the explanations are clear and eventually the important levels of verilog design are covered. So if read thoughtfully it is a very good intro to verilog, but beware the useless filler.
Rating: 
Summary: best intro to verilog on the market
Review: the verilog professional needs two books: one for introductory topics and easy examples, and one for difficult language issues.this book is the best introductory verilog book on the market, and is the one most frequently stolen from my office. this is the book i get for every new verilog learner, and it serves them well. moorby is more complete with respect to advanced topics, but more difficult to understand.
Rating:
Summary: good title, okay contents
Review: This book is suitable for its time, but the contents are more intended for Verilog models. It talks a lot about the Verilog syntax; however, the title mislead me - VERY LITTLE discussion about Verilog for Synthesis. There is only one chapter devoted to systhesis, and this chapter happens to be the LAST chapter of the book. Don't get me wrong. This is a good book for beginners in Verilog HDL. It is a "MIX-BAG" of syntax only for understanding (NOT synthesis). After reading this book, one should be familiar with the application of Verilog for Simulation and Modeling, but one may still have to get a synthesis book or training to further utilize the power of Verilog for FPGA or ASIC design (I am an FPGA designer). I gave it 3 stars due a misleading title and the fact that only a single chapter was devoted to synthesis topic. One topic bothers me. Why would someone use Verilog HDL to model the Transisor Level (he calls it the switch level)? Isn't this the reason SPICE programs were designed to do? Besides that, Verilog HDL is still YET to add ANALOG capabilities.
Rating:
Summary: A good intro to Verilog and a great Verilog PC simulator.
Review: This book provides good, methodical introduction to Verilog that is excellent for those familiar with programming languages. One of the best parts, though, is the great PC-based Verilog simulator included with the book (it's worth the price of the book by itself). The simulator allows you to try out small (and not-so-small) examples to really get a feel for the Verilog language.
Rating:
Summary: The Best Verilog Book for Beginners
Review: This book starts from very basic knowledge of Verilog. It assumes no prior knowledge of the language. It starts from explaining the different data types of Verilog with very clear examples. Then it shows you how to create a module and why is it important to divide your design into several modules. Then it teaches you how to create a circuit at gate level modeling. The schematics of the the code is given in the book, so you can clearly see the relationship between the schematics and its corresponding Verilog code. Then it moves to data flow modeling, again with very clear examples. After that, it moves to Behavioral Modeling. This the only book that gives me a very good understanding of always block, initial block, reg data type, and most importantly blocking and non blocking assignment. It has excellent example of how to create a state machine. The rest of the book teach you some tips that will make it easier for you to write your code. It also has some very good examples of how to create a testbench. Almost every example has its own testbench. So, you will learn how to create a testbench as you read the book from the very beginning. I only have 2 complains of the book. One is it doesn't tell you which part of the language is synthesizable until near the end of the book. Second is it doesn't tell you which part of the examples is the new features in Verilog 2001. This could be problematic if your simulator and synthesis tool does not fully support Verilog 2001. But other than that, I am fully satisfied. When I first learned Verilog, I browsed many other books. And this one is absolutely the best one. Without this book, I won't be able to finish my projects ahead of time with an A+. Good job Mr. Palnitkar!
Rating:
Summary: A very good introduction book.
Review: This book was a good introduction to Verilog. It was some what short in content in some areas, specifically timing analysis. It is easy to understand and the examples on disk run under any simulator. This book is a good learning tool and used with a good reference is a definite book to have on your desk.
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