Rating: 
Summary: Excellent
Review: An excellent book for a beginner like me. The first few chapter explains, the flow of the language-and helps you get a good hold.wonderful book, highly recommended.
Rating:
Summary: Excellent
Review: An excellent book for a beginner like me. The first few chapter explains, the flow of the language-and helps you get a good hold.wonderful book, highly recommended.
Rating: 
Summary: Clear, Simple and complete
Review: As a senior person new to Verilog I found this book to be well layed out and quick to read. I chose it because I found many positive references. Now I see why. It seems to be the best of the Verilog books.
Rating:
Summary: verilog HDL
Review: Excellent beginning work for the new EE grad. Having already accepted a position in ASIC design, I read this book over the summer and was able to immediately write complex test plans for new designs. Next challenge: design.Still keep the book on the shelf for reference although others try to borrow it.
Rating:
Summary: Good introductory book for Verilog
Review: Gives a very good introduction to Verilog HDL. Title is misleading because there isn't much synthesis covered. You won't get a whole lot of insight to the PLI either. If you don't know any Verilog, this book is a good place to start.
Rating: 
Summary: Buy the 1st edition
Review: I have chosen this book to teach for the last couple of years. Everything is organized and concise to the point. This is an excellent book. Only short coming is that it's a little out of date. This book is a must for those who desing ASIC with Verilog.
Rating:
Summary: Excellent Book
Review: I have chosen this book to teach for the last couple of years. Everything is organized and concise to the point. This is an excellent book. Only short coming is that it's a little out of date. This book is a must for those who desing ASIC with Verilog.
Rating:
Summary: Buy the 1st edition
Review: I looked at this book to learn Verilog 2001. This book is not it. The book doesn't cover the most basic constructs of Verilog 2001 such as always @(*) and the reduced verbosity of entity declarations. Also, the author does not cross-reference a feature with what standard supports it. This makes it worthless as a reference for both the new and old standard. If you want to learn Verilog 2001, wait for a better book. If you want to learn the old standard, buy his 1st edition.
Rating: 
Summary: good book but not complete
Review: like any beginner else, i felt that this book is to broad and not specific. The examples are to simple and the problems are to severe compare with they're examples. i've send an email to mr.Samir about the rest answer that not complete from his book, but till now there is no answer.
Rating:
Summary: Concentrates too much on behavioral code
Review: Like the other Verilog books I've read, this one seems to be a manual for those who wish to model rather than those who wish to synthesize actual circuits. The book concentrates too much on behavioral code and gate level design, neither of which are as important or as difficult as synthesizable code.
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