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Summary: Excellent book on verilog
Review: This book is good for beginners, it has a few good ideas in it. The Behavioral vs. RTL versions of the code is pretty useless, but the RTL vs. Simulation versions are useful. Getting a quick and dirty unit test bench up and running is a good idea. But DO NOT USE THE ASYNCHRONOUS FIFO. It does not work. If you are crossing clock boundaries, this is not the way to do it!
Rating: 
Summary: Some Good Points
Review: This book is good for beginners, it has a few good ideas in it. The Behavioral vs. RTL versions of the code is pretty useless, but the RTL vs. Simulation versions are useful. Getting a quick and dirty unit test bench up and running is a good idea. But DO NOT USE THE ASYNCHRONOUS FIFO. It does not work. If you are crossing clock boundaries, this is not the way to do it!
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Summary: Save your money
Review: This book lacks any real insight into design. All of the models complied are so simple any design engineer could write them. Although the author claims that the code is written with synthesis in mind most example are poorly coded. This book may be of help to someone who has never designed anything before, but I would not recomend implementing any of the code directly unless you don't care about efficient design
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Summary: The reviews about Verilog Designer's Library
Review: This book reviews the the Verilog Coding Technique in part one. It introduces the Genearl Coding, Behavioral Coding, and RTL coding technique. It makes reader understand how important the coding technique is. This book also explains synthesis issue and simulation issue. After these chapters introduction, the basic building block, state machines, some complex functions, error dection and correction, memory controller Verilog behaviour code and RTL code are introduced in further chapter. This book is for whom has a basic familiarity with Verilog language. It is very useful and valuable for hardware designer,hardware system engineer and student.
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Summary: value/price=almost zero
Review: This is a bad book, overall. I just pick 3 exemplary issues:.) The distinction between behavioural and RTL code in the examples is only there to double the number of pages. The listings are essentially the same, they differ in typically, like, 5 lines. Moreover, most synthesis tools would accept both programs and create the same circuit. .) creating Verilog code from 3 pages of C which could be done in 10 lines of Perl is not really state of the art. .) Worst of all: The asynchronous fifo does not protect the pointers on the clock domain boundary, so it is unusable in the real world. Either Bob Zeidman is not really up to date with his Verilog design skills, or it's the Dogbert priciple of "Beware the advice of successful people; they do not seek company."
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Summary: An indispensable starting point
Review: Tired of reinventing the wheel? Complete designs are provided for basic building blocks such as FIFOs, RAM controller, dual port RAM, State machines, etc. This book has proven an indispensable starting point.
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Summary: Best Verilog Book I've seen
Review: With many verilog books out there, this one has to be the best I've seen. It has real world modules, and explains what went into each module. This book is a MUST for any Beginner->Advanced ASIC designer. Highly recommended!!
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