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Rating: 
Summary: Very useful
Review: A clearly written, concise, and very helpful book.
Rating: 
Summary: The book was the best seller at the DAC conference, 1999.
Review: Functional verification /simulation techniques has been adequately covered in other books. This is the first book to focus exclusively on theory and applications of timing verification of ASICs and FPGAs. The fundamental concepts can be applied to ASICs, FPGAs and system-on-a-chip (SoC). The book highlights principles and techniques over specific tools. Therefore, the material presented in the book is EDA-tool independent. This book is to be used for self-study by practicing engineers as an introduction to timing verification. Design and verification engineers who are working with ASICs and FPGAs will find the book very useful. Upper -level undergraduate and graduate students in electrical engineering can use it as a reference book in design courses in timing analysis and related topics. Topic include:Clock definitions, multicycle paths, false paths, and phase-locked loops. Behavioral and structural RTL coding for timing Pre and post layout timing analysis Synthesis and timing constraints Timing analysis of FPGAs EDA timing tools
Rating: 
Summary: Good timing info, but a few Verilog errors
Review: Not a bad book for general introductry info on timing, but very little advanced detail for the experienced designer. There are a few errors in the Verilog examples. No big deal because little of the book is language specific. Good concepts presented but don't blindly follow any of the suggestions without really understanding them. Example 3.2 This module will not compile. - the sensitivity list is written like VHDL - he uses 'define statements then forgets to use a backtick when the definition is used Example 3.7 - Keyword is 'endmodule' not 'end module'
Rating:
Summary: A "must-have" book for practicing ASIC engineers
Review: The book has detailed information on timing issues of ASICs and FPGAs, such as pre and post layout timing analysis. Several comprehensive examples on timing analysis using different available STA tools makes the book a practical guide for verification engineers. The book also covers some RTL coding examples for timing, however it is made solely for timing verification not a book for learning HDL languages, therefore trying to criticize the programming part of the book as in previous review is irrelevant let alone trying to correct spelling.
Rating:
Summary: Very good book for the beginners
Review: This is a really good book for the beginners to understand the timing verification in ASIC flow.There are not many books in this area which explain things clearly.Most of them get lost in the syntax and modules of coding. 90% percent of ASIC design is done with synopsys tools and book authors tell more about the tool syntax than why they are there.This book has minimum of tool syntax.It is SIMPLE and that is its greatest quality.Most people who have reviewed the book have given good ratings.The one that is bad must be from an experienced person.This book is not for an expert in this field.
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