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Summary: The migration path for programmers
Review: Too many VHDL books dilute their point by trying to double as logic design texts. The problem is that VHDL is a complex (or "rich") language, and needs an intense focus of its own. This book does the best job I've seen.I've learned lots of languages, usually one or two a year. I know what to look for. I want a book that lays it all out clearly enough that I can find what I want. That includes complex data types, overloading, and especially configurability. VHDL really does have almost all the capabilities of a C-like language, plus a few more features, and the author has succeeded in making them accessible. Configurability deserves special attention - it is an explicit part of the VHDL language. It's a pre-Object-Oriented language but was developed when OO ideas were solidfying in the industry. Although it lacks OO flexibility, Ashenden does point out how "use" and "configure" can give a few of the same effects. Hardware description languages aren't like regular programming languages, and shouldn't be, and can't be. Still, they're not that different, either. Perhaps you're already a good programmer and already comfortable with digital system basics. If so, this may be the book to give you the language knowledge you need with minimal repetition of what you already know.
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Summary: The best VHDL reference to date
Review: Until Peter's next book comes out of course! I would give it 5 stars if I was just learning the VHDL language, but I'm actually trying to use VHDL for FPGA design and this book falls short in that regard. This book is really good at explaining the 'mechanics' of VHDL programming. It is an out growth of Peter's "Intro to VHDL" paper that was published on the web and it sort of shows. I really like the depth that it goes into, I wish it had the standard libraries in the appendix. (it doesn't) However, until getting Ashendon's book, all other VHDL texts were pretty opaque. The only thing this book does not have is a treatment of logic 'inference.' Since all VHDL compilers today "infer" (a fancy way of saying "guess") what logic would be able to implement a behavior, not understanding how those compilers guess makes it possible to write syntactically clean VHDL that doesn't synthesize any logic. To get a better handle on inference I'd recommend "HDL Chip Design" by Smith.
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