A Vhdl Synthesis Primer

Rating:
Summary: concise & practical
Review: In the modeling of digital logic with VHDL, sometimes you're wondering what difference between signals and variables in your code, what the literals of integer type really means in hardware, and why the signed and unsigned types are so convenient to use in many situations. Don't worry. J. Bhasker tells you what you want to know by good examples.

It's useful both for beginners and practicing engineers.

Rating:
Summary: Very informative
Review: It is a well written book , covering all aspects of VHDL.
This would be a must buy for students who would like
to start a career in VLSI, and also to those designers
who are not so familier with synthesis aspects of VHDL