The Anatomy of a High-Performance Microprocessor : A Systems Perspective

Rating:
Summary: Very good book, fantastic CD-ROM, a bit unbalanced.
Review: Being an ASIC designer, I bought this book to improve my understanding of the architecture and techniques used in high performance design. Looking at the book alone, I have a mixed feeling: the chapters that are dedicated inner workings of a processor completely satisfied my expectations. They include an in-depth description of all the main blocks that make a high-end processor or memory system work: register renaming, instruction decoding and scheduling, cache operation etc. This is really very excellent material! On the other hand, I consider the chapters dedicated to the system perspective to be of much lower quality and not in line with the title of the book. In a bit more than 100 pages, the author describes almost all other aspects of a modern PC, including Total-Cost-of-Ownership, Windows Qualification, Ethernet principles, Internet connectivity and even VESA Local Bus standard. Obviously, it is impossible to discuss such a wide range of topics in such a limited space. This flaw is compensated by a fantastic CD-ROM that contains an overwhelming library with a selection of research papers, articles from magazines, interviews and even a VHDL and Verilog simulator! Conclusion: I strongly recommend this book to anyone who wants to understand the secrets of a modern microprocessor. The removal of chapters about system aspects would have resulted in a 5 star rating.

Rating:
Summary: Really good book
Review: It contains a huge amount of interesting information and the CD-ROM that comes with it is just fascinating. This is a great book for learning about Microprocesser architecture.

Rating:
Summary: A good reference on high-performance microprocessor design
Review: This book is indeed an anatomy of high-performance processor design. In classic computer architecture books like Hennesey and Patterson's, it covers topics like out-of-order execution and speculative execution mechanisms, but only in abstract and algorithmic levels. This book uses an actual K6 microarchitecture as a foundation and explains these difficult concepts in RTL with pseudo code illustration. This can really help someone with purely ASIC background (knowledge of HDL) to fully understand the implementation of a RISC core with out-of-order and speculative execution capabilities