Rating: 
Summary: Excellent jump-start book for engineers!
Review: Anyone who understands C/pascal is going to love Ken's book. It's the perfect reference to sit next to your keyboard for a quick hands-on reference! Ken taught me in 1 minute how to create an array of cells in an FPGA simply via the TOC! In another minute I was implementing static-keys into a ROM'd lookup table. It could not have been easier. *Anyone trying to implement algorithms in Verilog should by this book*
Rating:
Summary: Excellent jump-start book for engineers!
Review: Anyone who understands C/pascal is going to love Ken's book. It's the perfect reference to sit next to your keyboard for a quick hands-on reference! Ken taught me in 1 minute how to create an array of cells in an FPGA simply via the TOC! In another minute I was implementing static-keys into a ROM'd lookup table. It could not have been easier. *Anyone trying to implement algorithms in Verilog should by this book*
Rating: 
Summary: Not so Bad (a biased opinion)
Review: I admit, the other reviewers have some good points, there are too many errors ... but overall I think the book holds up. This is not an academic book, I wanted to create something readable. I think some of my practical points are not available anywhere else. My intended audience is not ASIC designers (not the most fun crowd in the world) and College professors, but newbies and people looking for practical approaches to real world problems. To balance the few armchair critics, I know there are thousands of generally satisfied readers, so give it a try. I'm here and I'll take all the flogging and harrassment I deserve. To my critics, if you hate this book, wait until you see my next one.
All the best to the readers out there.
Rating: 
Summary: Don't waste your money!!!
Review: I received this book yesterday and read it in about 5 hours - I was very disappointed. in contains a number of typos and several mistakes. The listing 4-1 on p122 will synthesize a SYNCHRONOUS binary counter, i.e., all DFFs within count_out are clocked simultaneously with the same clk - its inside a process sensitive to clk. A ripple counter on the other hand has one DFF fed by clk and the other counters are fed by the Q or Q-bar output of the previous FF (where each FF is configured to divide its clock input by two). Often ripple counters are built using T flip-flops. For example, p594 "Digital Design, Principles and Practices", John Wakerly, 2nd Ed. pp353-p356 "Fundamentals of digital logic with VHDL design", Brown and Vranesic. In my opinion, the inclusion of illegible LeonardoSpectrum schematics is a total waste of space. The author could easily have commented on the complexity of the problem in cases where the book formatting would reproduce the schematic poorly. Alternatively, if the author needed the schematic version - redraw it! For a title that suggests real-world design I was disappointed. The book did contain some annecdotal experience which was interesting, but in terms of how to approach a real-world design with an example of such an approach, I found it lacking. For example, the only design of any substance in the text is an SRAM controller. However, there is no state diagram or ASM chart showing that the state machine was 'designed' or 'specified' prior to coding, and there are no timing diagrams or test bench to indicate that any simulation of the design was performed, and then there is no final analysis that shows the design met the setup/hold, etc requirements of whatever external SRAM was being used in the design. Those are the real-world issues that the author refers to in the text, but then never does himself. Also, the HDL pretty-printing is terrible. Two thumbs down! (I'm sending this book back)
Rating:
Summary: Don't waste your money!!!
Review: I received this book yesterday and read it in about 5 hours - I was very disappointed. in contains a number of typos and several mistakes. The listing 4-1 on p122 will synthesize a SYNCHRONOUS binary counter, i.e., all DFFs within count_out are clocked simultaneously with the same clk - its inside a process sensitive to clk. A ripple counter on the other hand has one DFF fed by clk and the other counters are fed by the Q or Q-bar output of the previous FF (where each FF is configured to divide its clock input by two). Often ripple counters are built using T flip-flops. For example, p594 "Digital Design, Principles and Practices", John Wakerly, 2nd Ed. pp353-p356 "Fundamentals of digital logic with VHDL design", Brown and Vranesic. In my opinion, the inclusion of illegible LeonardoSpectrum schematics is a total waste of space. The author could easily have commented on the complexity of the problem in cases where the book formatting would reproduce the schematic poorly. Alternatively, if the author needed the schematic version - redraw it! For a title that suggests real-world design I was disappointed. The book did contain some annecdotal experience which was interesting, but in terms of how to approach a real-world design with an example of such an approach, I found it lacking. For example, the only design of any substance in the text is an SRAM controller. However, there is no state diagram or ASM chart showing that the state machine was 'designed' or 'specified' prior to coding, and there are no timing diagrams or test bench to indicate that any simulation of the design was performed, and then there is no final analysis that shows the design met the setup/hold, etc requirements of whatever external SRAM was being used in the design. Those are the real-world issues that the author refers to in the text, but then never does himself. Also, the HDL pretty-printing is terrible. Two thumbs down! (I'm sending this book back)
Rating:
Summary: A waste of money. Sloppy first draft. Second half useless.
Review: I stopped reading it about halfway through when the book started telling me how to 'point and click' my way through dialog boxes for the author's favourite verilog tools. I purchased a Verilog book to learn Verilog. If I wanted to learn how to use some software, I would have read the User's Manual for that software.
It contained enough mistakes in the examples to make some examples difficult to understand. Verilog keywords were used in some examples without explaination. It did not cover all of the verilog language. For a newbie like myself I found this to be a big let down. I thought I was getting a book to learn verilog and how use it for real FPGAs. There was some annecdotal experience on real world FPGA design, but very brief. He could have spent the rest of the pages covering more Verilog instead of various verilog tools. Overall, I felt that the author put in about 25% of the effort required to write a good book on the subject. The editor used a common trick in publishing, where the font size of the text and the amount of whitespace per page is increased when an author submits much less than a book's worth of material. It fills up a book and makes the reader think that there is much more text in the book than there really is.
Rating:
Summary: A waste of money. Sloppy first draft. Second half useless.
Review: I stopped reading it about halfway through when the book started telling me how to 'point and click' my way through dialog boxes for the author's favourite verilog tools. I purchased a Verilog book to learn Verilog. If I wanted to learn how to use some software, I would have read the User's Manual for that software.
It contained enough mistakes in the examples to make some examples difficult to understand. Verilog keywords were used in some examples without explaination. It did not cover all of the verilog language. For a newbie like myself I found this to be a big let down. I thought I was getting a book to learn verilog and how use it for real FPGAs. There was some annecdotal experience on real world FPGA design, but very brief. He could have spent the rest of the pages covering more Verilog instead of various verilog tools. Overall, I felt that the author put in about 25% of the effort required to write a good book on the subject. The editor used a common trick in publishing, where the font size of the text and the amount of whitespace per page is increased when an author submits much less than a book's worth of material. It fills up a book and makes the reader think that there is much more text in the book than there really is.
Rating:
Summary: "A Fatherly Book For A Beginer"
Review: I was told about this book from my adviser Dr Shaob A Khan. This book is not only remarkable help for the sysnthesis on FPGA, but also a smooth and desciplined guide for the beginers of Verilog. Starting from the very first example of Overheat Alarm system this book keeps the reader in an enviorment where he gradually learns for the best.
Rating:
Summary: Good writing style
Review: I'm an analog design engineer with over 20 years of experience in industry. I want to add FPGA's to my bag of tricks, and I ran across Mr. Coffman's book via a search with Google. My book arrived a week ago and I am finding it to be just the kind of book I have been looking for. He has a good writing style, very easy to follow. I plan to invest many hours working through his examples with the included software. I have read other reviews of this book at this Amazon site. Some people are looking for an academic book on Verilog. Others are looking for a book that will teach them Verilog without spending the time programming and simulating (ie learning without doing homework). If you fall into either of these groups, this book is not for you. However, if you are an experienced engineer looking to learn about Verilog and VHDL through honest study and experimenting, then Mr. Coffman's book is an excellent choice to guide you through this process with a focus on the "real world". You also may find yourself chuckling at some of his commentary on the way
Rating:
Summary: Good writing style
Review: I'm an analog design engineer with over 20 years of experience in industry. I want to add FPGA's to my bag of tricks, and I ran across Mr. Coffman's book via a search with Google. My book arrived a week ago and I am finding it to be just the kind of book I have been looking for. He has a good writing style, very easy to follow. I plan to invest many hours working through his examples with the included software. I have read other reviews of this book at this Amazon site. Some people are looking for an academic book on Verilog. Others are looking for a book that will teach them Verilog without spending the time programming and simulating (ie learning without doing homework). If you fall into either of these groups, this book is not for you. However, if you are an experienced engineer looking to learn about Verilog and VHDL through honest study and experimenting, then Mr. Coffman's book is an excellent choice to guide you through this process with a focus on the "real world". You also may find yourself chuckling at some of his commentary on the way
| 
