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Rating: 
Summary: Good introduction to SystemVerilog for the experienced
Review: As an experienced hardware designer who wants to know what SV is all about, this book was great. It introduced the langauge in a natural way, explained what is synthesisable and is more readable than the LRM. You can also download the book examples from the author's website. This is the audience that this book aimed at and it hits the mark, especially as most designers can get the company to pay the high price of the book.
Downsides: there are some differences from the LRM, as this book was written before the final draft, and despite the book saying the chapter 10 complete design example simulates, it doesn't.
Rating: 
Summary: Good Overview but redundant
Review: Here are my opinions after buying and reading the book.
- If you are student / fresher who wants to "learn" System Verilog then skip this book. This book assumes that you already know Verilog well.
- This book deals only with design. Authors plan to come up with one more for Verification.
- If you have plenty of cash ($130 for design and $130 for verification book) or your rich company pays for your books then go ahead and add this book to your library. If not then read free LRM http://www.eda.org/sv/SystemVerilog_3.1a.pdf
- Practice, practice, practice. Just by reading Verilog books no one has become a good design/verification engineer.(...)Verilog won't become IEEE standard as it is. Thus this book will be superceded by a version which is slightly different anyway.
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